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eeNews Europe

System Check: What is next for industrial RF engineering?

Ready for the next System Check! Industrial RF design powers automation, wireless communications, and connected systems. We want to know which technologies you think will shape its future. Where will AI have the greatest impact? Past results We recently asked our community members about FPGAs and whether they work…

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SemiWiki Daniel Nenni

Executive Interview with Victor Lopez of RaiderChip

Victor Lopez is Co-Founder and CTO at RaiderChip, with over 20 years of experience in FPGA and ASIC design. Throughout his career, he has led the development of semiconductor IP and custom hardware solutions licensed by international companies in sectors such as defense, aerospace, automotive and professional video,…

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arXiv · Hardware architecture (cs.AR) Ali Mehrabi et al.

A Resource-Efficient and Precision-Scalable FPGA Accelerator for Spiking Neural Networks Using Minifloat Arithmetic

Spiking neural networks (SNNs) are well suited to event-driven edge intelligence, but the arithmetic complexity, memory footprint, and power consumption associated with conventional floating-point implementations can limit their deployment on resource-constrained hardware. This paper presents a precision-scalable and…

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arXiv · Hardware architecture (cs.AR) Hamza Kheddar

Reinforcement learning for hardware acceleration and system-level optimization on FPGA and integrated-circuit platforms: A survey

Reinforcement learning (RL) enables adaptive and autonomous decision-making in embedded, edge, and heterogeneous computing systems. Field-programmable gate arrays (FPGAs) and integrated circuits (ICs) offer low latency, energy efficiency, and architectural flexibility for RL deployment, while introducing challenges in…

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arXiv · Hardware architecture (cs.AR) Joseph Kurina et al.

A Combined Streaming FPGA Architecture for Client-Side CKKS Encoding and Encryption

Homomorphic encryption allows a computing service to process encrypted data, but the client must first encode and encrypt its inputs. Sharing hardware between floating-point encoding and modular encryption reduces area but requires those transform roles to execute at different times. We present a streaming FPGA…

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arXiv · Hardware architecture (cs.AR) Arnab A. Purkayastha et al.

Heuristic-Driven Resource Optimization for Decoupled Memory Channels on FPGAs

Determining OpenCL channel depths for Decoupled Access-Execute (DAE) architectures in High-Level Synthesis (HLS) is critical for balancing performance and hardware efficiency. Conventional static analysis tools often over-provision these memory channels to ensure performance safety, leading to significant resource…

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