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arXiv · Hardware architecture (cs.AR) Junhyeok Park et al.

HAWK: Heterogeneity-Aware KV Cache Transfer for Efficient GPU-NPU Phase-Disaggregated LLM Inference

Large language model (LLM) inference exhibits distinct computational characteristics across its two phases: prefill is compute-intensive, whereas decode is more memory-bound. As a result, AI accelerators achieve varying levels of efficiency across the two phases. GPUs are well suited to prefill, but are often…

arXiv · Hardware architecture (cs.AR) Zijun Zhao et al.

MX-Like Tensor Core for LLM Inference with NPU Integration via Hardware-Software Co-Design Exploration

Block-scaled quantization formats such as OCP Microscaling (MX) and NVFP4 have been widely adopted as efficient data formats for LLM inference. However, the design space of these formats spanned by shared scale, weight, and activation format combinations has not been systematically explored, and the joint…

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A New GPU, From Facebook ?!

Meta builds its own AI accelerators, and at Hot Chips 2026 it presents the next two: the MTIA 300 for training and the MTIA 400 for generative AI and recommendation. Recommendation compute at Meta grows 3x a year, and GPUs sit idle waiting on memory for those workloads. I also show the first two MTIA generations on…

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Inside Korea's AI Silicon // The AI Hardware Show S2E12

South Korea has quietly become one of the most active fronts in the AI chip race, and Sally Ward-Foxton and Ian Cutress are on the ground to find out why. In this episode of The AI Hardware Show, they break down five of the country's boldest AI silicon players — DeepX, HyperAccel, Mobilint, Furiosa AI, and Rebellions…

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[54] The Man Who Built OpenAI's First Chip

Today's sponsor is https://www.amtechmicro.com Richard Ho leads hardware at OpenAI. He joined Google's TPU program as one of its first engineers, built Anton supercomputers at D. E. Shaw before that, and now runs the team behind Jalapeño. He tells me how close he came to a blank cheque, why the team bet on wiring HBM…

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The Microwatt Chip Race // The AI Hardware Podcast S2E11

Forget the data center - the real AI action might be happening in microwatts. Sally Ward-Foxton and Ian Cutress dig into the tiniest AI chips on the market, from analog compute upstarts to ARM's revived Ethos NPU line, and debate why an "AI ASIC" isn't really an ASIC at all. Plus: a mysterious defense-linked startup…

IEEE Spectrum · Semiconductors Matthew S. Smith

How OpenAI Used Its Own LLMs to Design Its Jalapeño Chip

On 25 August, OpenAI fully unveiled Jalapeño, the company’s debut AI accelerator chip. Jalapeño delivers up to 13.4 petaflops of 4-bit compute and accesses 232 gigabytes of the most advanced memory available, linking to it at a blazing 15.4 terabytes per second. Benchmarks cited by OpenAI show that Jalapeño can reduce…

Samsung · Semiconductors Samsung Newsroom

Samsung and Mistral AI Announce Strategic Partnership for Intelligence-Driven Semiconductor Infrastructure

Samsung Electronics today announced it has entered into a strategic partnership with Mistral AI to enhance its semiconductor engineering and manufacturing capabilities that will reinforce its leadership in AI chip technologies. The announcement of the partnership was made during the state summit held in Paris between…

IEEE Spectrum · Semiconductors Samuel K. Moore

Stacking Chips Sideways Gives AI More Memory

GPUs and other big AI chips just can’t get enough memory. Today’s data center computers stack DRAM 12 dies high. But as memory makers try to build higher stacks to pack in more bits and bandwidth, experts worry this high bandwidth-memory (HBM) will trap enough heat to cook itself into oblivion. That will be especially…