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TechPowerUp AleksandarK

Intel "Raptor Lake Next" 16-Core and 20-Core CPUs Surface

Intel is actively planning the "Raptor Lake Next" chips as an update to its Socket LGA-1700 desktop processors. These chips are essential for PC buyers who are limited to the decade-old DDR4 memory standard due to the high prices of DDR5 memory, especially since the current Core Ultra "Arrow Lake" processors do not…

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TechPowerUp AleksandarK

TSMC A14 Node to Break Eight Years of SRAM Scaling Stagnation

TSMC, the world's largest and most advanced semiconductor manufacturer, has been grappling with stagnant progress in SRAM scaling for years. Since the launch of the N5 5 nm process in 2020, the size of the SRAM 6T bitcell has remained around 0.021 µm². While transistor density in logic elements has increased, memory…

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TechPowerUp AleksandarK

NVIDIA Cuts HBM4 Speed and NVLink Bandwidth Targets for "Vera Rubin"

NVIDIA has officially implemented changes across its "Vera Rubin" product line, reducing target specifications for memory and interconnect fabric. According to the updated product specification sheet, the first change involves HBM4 memory. Previously, NVIDIA used HBM4 with a speed of 11.7 Gbps per pin, which has now…

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Semiconductor Engineering Technical Paper Link

Vertical DRAM Stacking Expands Thermal Design Space Beyond HBM-on-GPU (imec)

Researchers at imec published “Beyond HBM-on-GPU: Thermal Design Envelope for 3D Volumetric DRAM-on-GPU Integration.” Summary: Researchers evaluated a 3D memory architecture that rotates DRAM dies vertically above a GPU and places cooling cavities between them as an alternative to conventional 2.5D HBM and…

gpumemory Saved copy
TechPowerUp AleksandarK

YMTC to Start Mass Production of LPDDR5X with 9,600 MT/s Speed

YMTC, known as a NAND Flash manufacturer, is reportedly preparing to start mass production of LPDDR5X memory. While it has been known for some time that YMTC plans to enter DRAM production alongside its main NAND Flash business, it was not widely known that the company had already begun low-scale manufacturing.…

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Semiconductor Engineering The SE Staff

Chip Industry Week In Review

CHIPS Act $389M to power chips, vertical GaN, materials; Micron's memory roadmap; Nvidia expands supply chain capacity; Tenstorrent raises $1.5B; China NAND fabs; 800V power for AI data centers; Intel advances Arizona fab; China orders +$35B in Nvidia GPUs. The post Chip Industry Week In Review appeared first on…

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arXiv · Hardware architecture (cs.AR) Hewen Zhang et al.

Verified DRAM Address Mapping Reverse Engineering with Threshold Sweep

We propose an end-to-end software pipeline for solving and validating DRAM address mapping functions on embedded LPDDR5 systems, and we instantiate it on embedded platforms. Starting from a large latency dataset of address pairs, the pipeline first builds a latency histogram and then performs a threshold sweep to…

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TechPowerUp DrUsmanSaleem

Dell CEO Says the Memory Shortage Will Get Worse in 2027

Michael Dell doesn't think the memory shortage is anywhere near over. Speaking with The Wall Street Journal, Dell's chairman and CEO said things will get worse next year, as the AI data center buildout keeps soaking up DRAM and HBM supply. According to him, the bottleneck for Dell isn't demand, since the company is…

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arXiv · Hardware architecture (cs.AR) Bipin Thapa Magar et al.

M3D-FLOW: A Monolithic 3-D-Stackable Processing-Near-DRAM Architecture for Generative Normalizing Flow Applications

Normalizing Flows (NFs) have shown strong results in generative modeling, recently reaching state-of-the-art image generation performance. However, their repetitive, sequential operations limit the computational and memory efficiency achievable with GPUs and TPUs. We propose M3D-FLOW, a novel monolithic 3D-stackable…

gpumemory Saved copy
arXiv · Hardware architecture (cs.AR) Bipin Thapa Magar et al.

Sustainable Processing-in-DRAM Integration and Replacement for Transformer Inference Servers

Processing-in-DRAM (PID) accelerators are emerging as a sustainable alternative to GPUs for transformer model inference. They bring compute to data, mitigate the memory bandwidth limitation, and reduce the overall energy footprint. Yet, carbon analysis of PID accelerators is covered for only a limited set of hardware…

gpumemory Saved copy
arXiv · Hardware architecture (cs.AR) Sanghyeok Han et al.

A Hybrid GPU and Processing-Near-Memory Architecture with Shared DRAM for Efficient Prefill-Decode Disaggregation

The growing adoption of large language models (LLMs) has significantly increased the compute and memory demands of inference serving. A key challenge arises from the mismatch between compute-bound prefill and memory-bound decoding: when executed together, the two phases interfere, while separating them via…

gpumemory Saved copy
arXiv · Hardware architecture (cs.AR) Yudong Pan et al.

3D-MoE: Complementarity-Guided Hardware-Software Co-Design for MoE Decode on 3D-Stacked NMP

Mixture-of-Experts (MoE) have become a mainstream way to scale Large Language Models (LLMs), because each token activates only a small subset of experts, reducing inference cost. However, MoE decode remains highly memory-bound and exhibits strongly skewed, time-varying expert loads. 3D-stacked DRAM near-memory…

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arXiv · Hardware architecture (cs.AR) Guangyuan Xu et al.

TileDRAM: Compiler-Controlled Tile-to-DRAM Layouts for 3D DRAM GPGPUs

Modern GPU compilers expose rich layout abstractions for mapping tensors to threads and on-chip resources, but compute-unit-local (CU-local) 3D DRAM architectures lack a corresponding abstraction for specifying how operand-tile data are arranged within the DRAM address space. Without such an abstraction, conventional…

gpumemory Saved copy
arXiv · Hardware architecture (cs.AR) Murali Emani et al.

Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains

The design space of modern AI/HPC systems has expanded rapidly across compute architectures, including GPUs, dataflow processors, and RISC-V accelerators; memory tech- nologies, including HBM, GDDR, and SRAM; and interconnects such as NVLink, UALink, Infinity Fabric, InfiniBand, Slingshot, and Ultra Ethernet. No…

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arXiv · Hardware architecture (cs.AR) Jinheng Li et al.

HBFSim: A Simulator for Exploring HBF in Memory Hierarchies for LLMs

High Bandwidth Flash (HBF) has recently emerged as a promising technology that provides terabyte-scale accelerator-local capacity at bandwidths approaching HBM, with a potential cost-per-bit advantage over HBM. However, its NAND foundation brings long latency, out-of-place updates, and finite write endurance directly…

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arXiv · Hardware architecture (cs.AR) Yilong Zhao et al.

GUMPIM: Unitary and Malleable Memory for Processing-in-Memory with Guaranteed PIM Pages

DRAM-based Processing-in-Memory (PIM) addresses the "memory wall" by executing computations directly inside main memory. However, memory interleaving and virtual memory limit contiguous data size visible to PIM units, constraining PIM task granularity. To mitigate this, existing PIM systems drastically isolate PIM…

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TechTechPotato TechTechPotato

More Details on Broadcom's Beast XPU

Broadcom's Beast XPU is coming in 2028 with 16 HBM stacks and 8 compute dies on a single package, but how do you actually build something that big? At OCP Taiwan, Broadcom's VP of ASIC products gave a talk on 3.5D heterogeneous "scale-in" packaging, covering face-to-face bonding, 8x higher thermal density, chiplet…

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TechTechPotato TechTechPotato

[54] The Man Who Built OpenAI's First Chip

Today's sponsor is https://www.amtechmicro.com Richard Ho leads hardware at OpenAI. He joined Google's TPU program as one of its first engineers, built Anton supercomputers at D. E. Shaw before that, and now runs the team behind Jalapeño. He tells me how close he came to a blank cheque, why the team bet on wiring HBM…

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