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arXiv · Hardware architecture (cs.AR) Debleena Das et al.

Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors

Functional verification of Register-Transfer Level(RTL) designs has become a critical bottleneck in modern semiconductor development, often consuming the majority of project resources. Debugging, in particular, remains an especially time-consuming task, requiring careful analysis of simulation traces or…

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arXiv · Emerging technologies (cs.ET) Rodion Novkin et al.

NN-Based Transistor Modeling for Ultra-Fast SPICE Simulation and Standard Cell Library Characterization

Neural network (NN)-based transistor models have proven to be a promising solution to accelerate device modeling. Although these models demonstrated remarkable speedup in circuit simulations, they were not rigorously tested in complex tasks within standard EDA tool flows for chip design, which require very high…

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arXiv · Hardware architecture (cs.AR) Daniel Keller et al.

Stop Paying by the Letter: Accelerating Full-Chip RTL Simulation with Host-Side Tokenized Logging

Firmware diagnostic logging (printf) is an essential debug instrument in full-chip SoC design verification, yet it imposes a heavy tax on cycle-accurate RTL simulation: formatting a 30-character, 1-argument message on a simulated CPU and serializing it through an MMIO aperture costs 3.04 to 15.23 $μ$s per call (15.27…

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arXiv · Hardware architecture (cs.AR) Siddharth Patel et al.

Learn the Interface, Not the Implementation: Output Representation Dominates Training Regime in LLM-Based RTL Generation

Large-language-model register-transfer-level (RTL) generation has concentrated on how to train the model: fine-tuning, continued pre-training, and reinforcement learning from a verifier. We argue this is the second-order question. On a bounded, formally specifiable task of generating single-error-correcting,…

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arXiv · Hardware architecture (cs.AR) Danila Gorodecky

MAC units for a 2x2 int8 systolic array on Tiny Tapeout

We take the multiply-accumulate (MAC) unit of an open-source 2$\times$2 int8 systolic array taped out on Tiny Tapeout (GF180 process) and propose two replacements. The first one, \emph{hybrid}, uses a different arithmetic structure for each row of the array. It reduces the logic area of one MAC unit by 4--6\% and of…

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TechTechPotato TechTechPotato

Agentic AI and Why Everyone Wants CPUs Again

Agentic AI runs its tools on the CPU, and no vendor tells you how many cores an agent needs. In this keynote at the Design Automation Conference, I compare AMD Venice, Intel Xeon 6, the Arm AGI CPU and Nvidia Vera, then follow the problem down into advanced packaging, CFETs and thermals. You also hear what EDA tools…

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