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EE Times Pablo Valerio

Arm Comments on Jury Decision in Qualcomm Trial

Arm's Ami Badani cites the $2 nominal damages award as validation, while chip design experts point to open architectures such as RISC-V as the long-term alternative for AI workload flexibility. The post Arm Comments on Jury Decision in Qualcomm Trial appeared first on EE Times.

arXiv · Hardware architecture (cs.AR) Emanuele Venieri et al.

Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads

RISC-V is emerging as a candidate architecture for high-performance computing (HPC), but its competitiveness against established x86 and Arm processors remains difficult to assess because existing studies use different platforms, workloads, and methodologies, and rarely consider energy efficiency. Our work provides an…

arXiv · Hardware architecture (cs.AR) Debleena Das et al.

Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors

Functional verification of Register-Transfer Level(RTL) designs has become a critical bottleneck in modern semiconductor development, often consuming the majority of project resources. Debugging, in particular, remains an especially time-consuming task, requiring careful analysis of simulation traces or…

dashboard.xiangshan.cc via r/hardware /u/SERIVUBSEV

Open Source high performance RISC-V CPU "Kunminghu v3" has reached SPECint06/GHz > 21.7 on nightly build this week, which is better than ARM's V3, Intel's Sapphire Rapids and close to Zen 5 in terms of performance.

This dashboard has weekly and nightly performance regressions for those interested. On nightly build, Kunminghu v3 has hit GEOMEAN(INT) of 21.706 with gcc, which keeps going up as the platform nears validation and release phase in Q1 2027. SPECint06/GHz on xscc is 21.924. SPECint17/GHz is 2.321, which also compares…

arXiv · Hardware architecture (cs.AR) Murali Emani et al.

Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains

The design space of modern AI/HPC systems has expanded rapidly across compute architectures, including GPUs, dataflow processors, and RISC-V accelerators; memory tech- nologies, including HBM, GDDR, and SRAM; and interconnects such as NVLink, UALink, Infinity Fabric, InfiniBand, Slingshot, and Ultra Ethernet. No…

TechTechPotato TechTechPotato

This is why I love my job

Day one of the AI Infrastructure Summit drew 9,000 people and a show floor twice the size of last year. I interviewed David Patterson on stage for the day one keynote, and he points to memory as the next limit for AI systems. On my floor walk I cover new liquid cooling tech, Quake on RISC-V, more chips, and why…

The Chip Letter Babbage

RISC-V : What Really Matters

Readers may have seen the recent post from Dmitri Grinberg RISC-V: They Should Have Known Better which sets out, at some length, his criticisms of the ISA.

Hot Chips · YouTube talks hotchipsvideos

HC2025-S2: Security

Session 2, Hot Chips 2025, Monday, August 25, 2025. Chair: Greg Papadopoulos, NEA Presto: A RISC-V-Compatible SoC for Unified Multi-Scheme FHE Acceleration over Module Lattice Luchang Lei & Hongyang Jia, Tsinghua University Azure Secure Hardware Architecture: Establishing a Robust Security Foundation for Cloud…

Hot Chips · YouTube talks hotchipsvideos

HC2025-S1: CPUs

Session 1, Hot Chips 2025, Monday, August 25, 2025. Chair: Gabriel Southern, Qualcomm Cuzco: A High-Performance RISC-V RVA23 Compatible CPU IP Ty Garibay & Shashank Nemawarkar, Condor Computing PEZY-SC4s: The Fourth Generation MIMD Many-core Processor with High Energy Efficiency and Flexibility for HPC and AI…