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Semiconductor Engineering Technical Paper Link

Security-Aware Layer Mapping Reduces Fault Vulnerability In 3D Compute-In-Memory (ASU, U. of Maryland)

Researchers at Arizona State University and University of Maryland published “SEAL: Multitenant Security-Aware Layer Mapping for Heterogeneous 3-D CiM Accelerators.” Abstract: “Heterogeneous 3-D compute-in-memory architectures can combine different memory technologies across stacked tiers to accelerate deep neural…

arXiv · Emerging technologies (cs.ET) Théo Dupuis et al.

Local learning with imperfect analog synapses

Analog in-memory computing delivers efficient neural network inference at the edge, but systems deployed in non-stationary environments may need to adapt in situ to locally acquired data. Backpropagation faces two structural obstacles here. Its global error transport lets stochastic write errors compound across…

arXiv · Hardware architecture (cs.AR) Yilong Zhao et al.

GUMPIM: Unitary and Malleable Memory for Processing-in-Memory with Guaranteed PIM Pages

DRAM-based Processing-in-Memory (PIM) addresses the "memory wall" by executing computations directly inside main memory. However, memory interleaving and virtual memory limit contiguous data size visible to PIM units, constraining PIM task granularity. To mitigate this, existing PIM systems drastically isolate PIM…

arXiv · Emerging technologies (cs.ET) Mehmet Aktukmak et al.

Closed-Form Optimal Weight Splitting for Matrix-Vector Multiply on Noisy In-Memory Accelerators

Analog in-memory computing performs the matrix-vector multiplications of neural networks directly inside the memory array, which saves time and energy. But each memory cell stores only a few levels and is noisy, so one cell cannot hold a weight precisely. The standard fix is to split each weight across several cells,…

arXiv · Emerging technologies (cs.ET) Fabian Seiler et al.

Cross-Layer Co-Design of Low-Latency Stateful Logic Adders with Printed Memristors

Data movement between memory and processing units remains a major bottleneck in data-centric systems. Memristive Stateful Logic (SL) addresses this problem by performing Boolean operations directly on stored resistive states. However, arithmetic efficiency depends jointly on the device-supported logic primitive set,…

arXiv · Emerging technologies (cs.ET) Patrick Miller et al.

PRIM: Energy- and Endurance-Aware Compiler Optimization for Digital Compute in Non-volatile Memory

Compute-in-Memory (CiM) is an alternative computing paradigm that circumvents the memory bandwidth bottleneck. Variants utilizing non-volatile memory cells (NVCiM) to perform Boolean operations directly within memory arrays offer significant density and energy-efficiency advantages. Fully realizing this potential,…

Hot Chips · YouTube talks hotchipsvideos

HC2025-S7: Machine Learning 1

Session 7, Hot Chips 2025, Tuesday, August 26, 2025. Chair: Ronny Krashinsky, NVIDIA Memory: (Almost) the Only Thing That Matters Mark Kuemerle, Marvell Corsair - An In-memory Computing Chiplet Architecture for Inference-time Compute Acceleration Sudeep Bhoja, d-Matrix UB-Mesh: Huawei’s Next-Gen AI SuperComputer with…