Silicon Feeds
Researchers at the Technical University of Munich and Indian Institute of Technology Kanpur published “Self-Heating and Parasitic Effects in Multi-Tier CFET Design.” Abstract Excerpt: “We study the impact of self-heating effects (SHEs) and middle of line (MOL) and back-end of line (BEOL) induced parasitics on…
Researchers at Technical University of Munich published “NN-Based Transistor Modeling for Ultra-Fast SPICE Simulation and Standard Cell Library Characterization.” Abstract: “Neural network (NN)-based transistor models have proven to be a promising solution to accelerate device modeling. Although these models…
A process sequence for SRAM and logic that delivers higher performance through larger effective channel width and improved electrostatics at smaller nodes. The post How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å appeared first on Semiconductor Engineering.
666 Million Transistors Per Square Millimeter
A closer look at Intel's current situation. Can Panther Lake, Clearwater Forest and Intel's 18A process node start a "Made in USA" microchip comeback? Become a supporter on Patreon: https://www.patreon.com/user?u=46978634 Follow me on Twitter/X: https://x.com/highyieldYT Follow me on bsky:…
Samsung Electronics, a world leader in advanced semiconductor technology, today announced that it will provide turnkey semiconductor solutions using the 2-nanometer (nm) foundry process and the advanced 2.5D packaging technology Interposer-Cube S (I-Cube S) to Preferred Networks, a leading Japanese AI company. By…
Samsung Electronics, a world leader in advanced semiconductor technology, today announced that it will deliver the next generation Arm® Cortex™-X CPU optimized on Samsung Foundry’s latest Gate-All-Around (GAA) process technology. This initiative is built on years of partnership with millions of devices shipped with…