Testing Silicon Photonics At Scale
New test requirements include fiber alignment, coupling efficiency, polarization management, and optical instrumentation. The post Testing Silicon Photonics At Scale appeared first on Semiconductor Engineering.
New test requirements include fiber alignment, coupling efficiency, polarization management, and optical instrumentation. The post Testing Silicon Photonics At Scale appeared first on Semiconductor Engineering.
Pinpointing failures, ensuring known-good optical engines, and controlling test costs become increasingly critical as photonics moves into advanced packages. The post Bringing Down Test Costs For Co-Packaged Optics appeared first on Semiconductor Engineering.
Researchers from Institute of Science Tokyo, Yokohama National University, AIST, and Photonics Electronics Technology Research Association (PETRA) published a technical paper titled “Reduced-DSP 200G/λ Low-Voltage Slow-Light Silicon Modulator Enabled by Built-In EO Equalizer.” Abstract Excerpt: “Multi-Tb/s optical…
Today we are taking a look at a network-focused industrial mini-PC from Qotom, the Q51551UT. The small box goes big on networking, with 10 Ethernet ports that support data rates as high as 10Gbps The post Qotom Q51551UT 4x 10GbE and 6x 2.5GbE Mini PC Review appeared first on ServeTheHome.
SEMICON West 2026: Advanced packaging, photonics, test, and AI are increasingly intertwined; very different conversations ahead. The post Chip Scaling Moves Beyond The Transistor appeared first on Semiconductor Engineering.
Migrating transformer inference to the edge requires sustainability considerations that encompass both operation and manufacturing, rather than operational energy alone. Silicon photonics enables high-bandwidth, low-energy matrix multiplication; however, existing microring-resonator-based Dot Product Unit (DPU)…
The design space of modern AI/HPC systems has expanded rapidly across compute architectures, including GPUs, dataflow processors, and RISC-V accelerators; memory tech- nologies, including HBM, GDDR, and SRAM; and interconnects such as NVLink, UALink, Infinity Fabric, InfiniBand, Slingshot, and Ultra Ethernet. No…
I walk the show floor at TSMC's Open Innovation Platform (OIP) event in the Bay Area. It's a one-day conference where TSMC puts its partners front and centre. We stop by Cadence, Samsung, SK hynix, Synopsys and GUC to see what's next for HBM thermals, co-packaged optics, UCIe 2.0 and AI-assisted chip design. If you've…
We're at the final day of the AI Infrastructure Summit, and the booths come down around me as I walk. You get Dnotita's vector database ASIC back from the fab, SK Hynix mocking up high bandwidth flash, Marvell showing photonics, and a 30 watt box running 120 billion parameters for 2,100 dollars. Ruby Goodall, who runs…
Session 4, Hot Chips 2025, Monday, August 25, 2025. Chair: Sherry Xu, Microsoft Intel Mount Morgan Infrastructure Processing Unit (IPU) Patrick Fleming, Intel AMD Pensando™ Pollara 400 AI NIC Architecture and Application Kevin Chu, AMD NVIDIA ConnectX-8 SuperNIC: A Programmable RoCE Architecture for AI Data Centers…
How a small Belgian town became the center of semicondcutor innovation. From High-NA EUV to silicon photonics. A closer look at imec. Become a supporter on Patreon: https://www.patreon.com/c/user?u=46978634\ Follow me on X: https://x.com/highyieldYT Follow me on bsky: https://bsky.app/profile/highyield.bsky.social…